The designs for many semiconductor processing facilities involve a process chamber where a semiconductor wafer is processed (e.g., etched or subjected to deposition) by a plasma. The designs often include an electrostatic chuck (or ESC) to clamp the semiconductor wafer during such processing, through the use of an electrical pole pattern in the electrostatic chuck. The design of the electrical pole pattern can have an effect on the uniformity of the clamping.
Once the processing is complete, the semiconductor wafer is separated or de-chucked from the electrostatic chuck so that it can be removed from the process chamber. However, residual electrostatic charge might remain, making efficient separation difficult. Here again, the design of the electrical pole pattern can have an effect on the efficiency of such separation.
To address the problem of residual electrostatic charge and to assist with process automation, among other things, some designs for semiconductor processing facilities include lift pins that raise the semiconductor wafer off the electrostatic chuck into a position where the semiconductor wafer can be retrieved with a robotic arm. Of course, if the force generated by such lift pins is not monitored and controlled, the lift pins can damage or even break the semiconductor wafer. In this regard, co-owned U.S. Pat. No. 6,646,857 (hereby incorporated herein by reference) describes, among other things, a group of lift pins that are connected in a yoke arrangement and that are coupled to a feedback loop.